Please give a lot of attention and participation from the members of the Mechanical Engineering department.

▣ Title: Non Conductive Film Analysis Using Cure Kinetics and Rheokinetics for Gang Bonding Process for 3DIC TSV Packaging

▣ Speaker: 문지영 책임연구원

▣ Affiliation: 삼성전자

▣ Date: 2022. 9. 30.(Fri) 13:30

▣ Venue: 제2공학관 B040호

▣ Host: 황정호 교수

▣ Abstract

Gang bonding process (GBP) using thermal compression bonder (TCB) is being developed recently as a means to massively stack multi chips. However, the GBP using the TCB has a difficulty in misalignment of stacked chips due to the difference in thermal expansion rate on the bonding head and the top surface of the chip. To overcome this problem, we have developed a facility for gang bonding without misalignment by thermal expansion of overhead. For bonding between chip and chip, non-conductive film (NCF) was used for the test vehicle. To achieve good quality bonding, wetting should occur on solder bumps and pads that connect chips and chips. For this, the NCF film must reach the lowest viscosity before solder bump melt and when the solder bump melts before the NCF cured. In addition to curing behavior between NCF and solder bump, press strength and time are also the core of the process. Therefore, a more detailed process for GBP is required than the existing process of the TCB method in the past. The design the optimal process for GBP only by experiment is timing-consuming and expensive. Therefore, we simulated the curing behavior of NCF and designed the customized process of the GBP. Firstly, the curing behavior of NCF was measured using the differential scanning calorimetry (DSC) and cure-kinetics was analyzed by building Kamal's model. Secondly, the viscosity behavior of NCF was measured using Rheometer and rheokineics was analyzed by constructing Macosko's model. Through this built model, NCF behavior was predicted during the gang manufacturing process using GBP and a suitable process was designed. We could find the optimal process through D.O.E in the designed process, and we checked the perfect wetting between solder bump and pad and the proper gap height between chip and chip.